1. Field of the Invention
This invention relates generally to a cache memory unit utilized by a data processing system and more particularly to a buffer stage between the cache memory and the main memory unit.
2. Description of the Prior Art
It is known in the prior art to utilize a cache memory unit to provide improved performance in a data processing unit. The performance of a data processing unit is determined, at least in part by the time required to retrieve data from the system main memory unit. The period of time required to retrieve data from the main memory can be minimized by implementing these circuits in the technology currently providing the highest speed. Because of the increasing memory requirements of modern data processing systems, this partial solution can be unacceptably expensive. In addition, delays caused by the physical distance between the central processing unit and the main memory can be unacceptable.
Because of these and other considerations, it has been found that a cache memory unit, associated with the central processing unit, provides a satisfactory compromise for providing the central processing unit with a requisite data availability. The cache memory unit is a high speed memory of relatively modest proportions which is conveniently located in relation to the central processing unit. The contents of the cache memory are selected to be those for which there is a high probability that the central processing unit will have an immediate requirement. To the extent that the algorithms of data processing system have transferred data required by the central processing unit from the main memory to the cache memory unit prior to the actual requirement by the central processing unit, the manipulation of data by the data processing system can be efficiently accomplished.
However, the transfer of the data from the main memory to the cache memory can be complicated. In the modern data processing system, an interface unit, which can be referred to as a system interface unit, can be interposed between the main memory and the central processing unit. The system interface unit is in effect a complex electronic switch controlling the interchange of data between the main memory (which may comprise several independent units), the central processing unit, and peripheral devices, which may be utilized in entering data into or retrieving data from the data processing unit. Thus the circuits in the system interface unit necessary to process the data transfer between the main memory and the cache memory may be unavailable, at least temporarily. Similarly, the central processing unit may have initiated activity in the cache memory unit which would similarly render the cache memory temporarily incapable of participating in the data transfer.
In situations where the two units or resources in a data processing system can be independently unavailable for data processing activity, such as a data transfer, it is known in the prior art to provide circuitry, which interrupts present activity of the required units or which prohibits future activity of the two units according to predetermined priority considerations, thereby freeing the resources or units of the data processing system for execution of the data transfer. This type of resource reservation can impact the overall efficiency of the data processing system by delaying execution of certain data mainpulations at the expense of other types of manipulations.
It is also known in the prior art to provide circuitry to permit the partial execution of a data transfer, a storing of the data at an intermediate location and then the completion of the execution at a later time, i.e., when the system resource becomes available. Thus, a buffering between the main memory unit and the cache memory unit can be accomplished, permitting the two units to operate in a generally independent manner. This type of data manipulation execution has the disadvantage that, after completion, the succeeding data transfers are again limited by the availability, prior to continuation of the sequence of data transfers, of each resource necessary to the completion of the data transfer.
It is therefore an object of the present invention to provide improved transfer of data between a main memory unit and a central processing unit of a data processing system.
It is a further object of the present invention to provide improved transfer of data between a main memory unit and a cache memory unit in a data processing system.
It is still a further object of the present invention to provide a buffer stage, associated with the cache memory unit which controls the transfer of information between the main memory unit and the cache memory unit.
It is a more particular object of the present invention to provide a buffer stage between the cache memory and the system interface unit.
It is still another particular object of the present invention to provide a buffer stage associated with the cache memory which permits sequential execution of data transfer activity between the system interface unit and central processing unit.
It is yet another object of the present invention to provide a buffer stage associated with the cache memory unit which permits sequential execution of data transfer instructions stored in the buffer stage while permitting execution of the activity involving the cache memory unit and the activity involving the system interface unit to be completed independently for the stored instructions.